My invention relates to frequency synthesizers using a phase locked loop, and particularly to such frequency synthesizers having modulation applied to both the reference oscillator and the voltage controlled oscillator.
In some frequency synthesizers using a phase locked loop, the modulation frequencies must cover the range of a few Hz up to several thousand Hz. An example is in a radio transmitter which is frequency modulated with low frequency signalling tones (20 Hz for example) and with higher frequency voice signals (such as 200 to 3000 Hz). Such synthesizers using a phased lock loop are known in the art, one example being U.S. Pat. No. 3,622,913 granted Nov. 23, 1971. In such prior art synthesizers, the modulated reference oscillator output is applied directly to the phase detector, and satisfactory operation is provided. However, where the modulated reference oscillator frequency must be divided to a lower frequency, a phase shift or time delay is introduced to the divided oscillator frequency which is applied to the phase detector. This presents a real problem in that the reference oscillator is usually crystal controlled and normally has an output in the MHz range for stability. This output must be divided by a factor of 1,000 or more before being applied to the phase detector. The divider circuit introduces significant time delay. However, in the prior art synthesizers, the modulated voltage controlled oscillator output is not subjected to an effective time delay, even though this output is multiplied or divided before being applied to the phase detector. Thus, the time difference between the modulated reference oscillator signal applied to the phase detector and the modulation signal applied to the voltage controlled oscillator causes significant distortion in the voltage controlled oscillator output from the phase locked loop.